The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having an improved semiconductor body with elements such as memory cells of a random access memory (RAM) device, each memory cell having one transistor and one capacitor.
A dynamic RAM device is known as one semiconductor memory. A conventional semiconductor body of this memory comprises an intrinsic gettering wafer (i.e., an IG wafer) which has a gettering effect obtained from microdefects formed inside a semiconductor substrate (wafer) whose surface region is free from defects. Another typical semiconductor body is an epitaxial wafer wherein a high-resistance semiconductor epitaxial layer is grown on a low-resistance semiconductor substrate. An IG wafer has a gettering effect inside. The gettering effect will not be lost in the fabrication process of a semiconductor memory, thereby preventing oxidation-induced stacking faults (OSF). A semiconductor memory having such an IG wafer can effectively prevent junction leakage and the like. In a memory having an epitaxial wafer, since the electric resistance of the substrate is very low, the lifetime of carriers in the substrate can be rendered extremely short. For this reason, the diffusion length of the electrons accidentally generated in the substrate can be decreased, thus prolonging the pause time.
There has been recently proposed a dynamic RAM device having a two-layer electrode which utilizes a semiconductor body with the advantages of both the IG and epitaxial wafers. A memory cell of this device will be described with reference to FIG. 1. Reference numeral 1 denotes a low-resistance p.sup.+ -type IG wafer having microdefects 2 inside. A p.sup.- -type single-crystal semiconductor layer 3 is formed by epitaxial growth on the IG wafer 1. The IG wafer 1 and the semiconductor layer 3 constitute a semiconductor body 4. A field oxide film 5 is selectively formed on the surface of the semiconductor layer 3. A p-type inversion preventive layer 6 is formed in the semiconductor layer 3 to extend underneath the field oxide film 5. A thin oxide film 7 is formed in an island region of the semiconductor layer 3 which is isolated by the field oxide film 5. A capacitor electrode 8 of polycrystalline silicon is formed on the oxide film 7. One end of the electrode 8 extends on the field oxide film 5. An n-type layer 9 is formed in the semiconductor layer 3 to extend underneath the capacitor electrode 8, and a thick oxide film 10 is formed to cover the capacitor electrode 8. Reference numeral 11 denotes a transfer gate electrode of polycrystalline silicon. Part of the transfer gate electrode 11 is located in the island region, and one end thereof extends on the oxide film 10 covering the capacitor electrode 8. A gate oxide film 12 is sandwiched between the gate electrode 11 and the island region. An n.sup.+ -type layer 13 as a bit line is selectively formed on the island region between the field oxide film 5 and the gate oxide film 12. A thick oxide film 14 is formed to cover the transfer gate electrode 11. In addition, an insulating interlayer 15 is formed to cover the oxide films 5, 10 and 14. An Al wiring strip 17 is formed on the insulating interlayer 15 so as to electrically contact the n.sup.+ -type layer 13 through a contact hole 16. A protective film 18 of an insulating material is formed to cover the entire surface of the resultant structure. In this dynamic RAM device, OSF and shallow pits are decreased by the IG effect to improve the performance of the semiconductor body 4.
However, in the semiconductor body 4 having such a dynamic RAM device structure, because the difference between the impurity concentrations of the p.sup.+ -type IG wafer 1 and the p.sup.- -type single-crystal semiconductor layer 3 is large, a potential barrier is formed at the p.sup.+ -p.sup.- junction. As a result, when .alpha.-rays become incident on the memory cell of the dynamic RAM device and electrons are accidentally generated in the p.sup.- -type single-crystal semiconductor layer 3, as shown in FIG. 2, the electrons are reflected at the interface between the semiconductor layer 3 and the IG wafer 1 and are returned to the semiconductor layer 3, thereby preventing diffusion and gettering of the IG wafer 1. For this reason, electrons reach under the capacitor electrode 8 formed on the semiconductor layer 3 and so cause data inversion. Therefore, the ratio soft errors caused by .alpha.-rays in the dynamic RAM device having the semiconductor body 4 become worse than those of the conventional RAM device having an IG wafer.
On the other hand, a complementary metal oxide semiconductor integrated circuit (CMOS-IC) having the semiconductor body described above is also known. This CMOS-IC will be described with reference to FIG. 3.
Reference numeral 21 denotes an n.sup.+ -type IG silicon wafer having a number of microdefects 22 therein. An n.sup.- -type single-crystal silicon layer 23 is formed by epitaxial growth on the IG silicon wafer 21. The IG silicon wafer 21 and the silicon layer 23 constitute a silicon body 24. A p-type well region (i.e., p-well) 25 is selectively formed in a surface layer of the silicon layer 23. A field oxide film 26 is selectively formed in the surface of the n.sup.- -type silicon layer 23. An n.sup.+ -type inversion preventive layer and a p.sup.+ -type inversion preventive layer (not shown) are respectively formed at portions of the n.sup.- -type silicon layer 23 below the field oxide film 26 and in the p-well 25, respectively. P.sup.+ -type source and drain regions 27.sub.1 and 28.sub.1 electrically insulated from each other are formed in an island region of the silicon layer 23 which is isolated by the field oxide film 26. An n.sup.+ -type diffusion region 29.sub.1 is formed in the island region of the n-type silicon layer 23 which is adjacent to the source region 27.sub.1. The n.sup.+ -type diffusion region 29.sub.1 serves to bias the silicon layer 23. A polycrystalline silicon gate electrode 31.sub.1 is formed on a gate oxide film 30 which is formed on a portion of the silicon layer 23 including the channel region between the source and drain regions 27.sub.1 and 28.sub.1. n.sup.+ -type source and drain regions 27.sub.2 and 28.sub.2 electrically insulated from each other are formed in the island region of the p-well 25 which is isolated by the field oxide film 26. A p.sup.+ -type diffusion region 29.sub.2 is formed in the island region of the p-well 25 which is adjacent to the source region 27.sub.2 so as to bias the p-well 25. A polycrystalline silicon gate electrode 31.sub.2 is formed on the gate oxide film 30 formed on the island region of the p-well 25 which includes the channel region between the source and drain regions 27.sub.2 and 28.sub.2. An insulating interlayer 32 is formed to cover the silicon layer 23 including the gate electrodes 31.sub.1 and 31.sub.2. An Al source wiring strip 33 is formed on the insulating interlayer 32 so as to form an electrical contact with both the p.sup.+ -type source region 27.sub.1 and the n.sup.+ -type diffusion region 29.sub.1 through respective contact holes. An Al drain wiring strip 34 is formed on the insulating interlayer 32 so as to form an electrical contact with the drain regions 28.sub.1 and 28.sub.2 through respective contact holes. Al gate wiring strip 35 is formed on the insulating interlayer 32 so as to form an electrical contact with the gate electrodes 31.sub.1 and 31.sub.2 through the respective contact holes. An Al source wiring strip 36 is formed on the insulating interlayer 32 so as to form an electrical contact with the n.sup.+ -type source region 27.sub.2 and the p.sup.+ -type diffusion region 29.sub.2 through the respective contact holes. Note that the Al gate wiring strip 35 is bonded to a Vin terminal, the Al drain wiring strip 34 is bonded to a Vout terminal, the Al source wiring strip 33 of the p-channel MOS transistor is bonded to a V.sub.DD terminal, and the Al source wiring strip 36 of the n-channel MOS transistor is bonded to a V.sub.SS terminal.
However, the CMOS-IC shown in FIG. 3 is prone to a latch-up phenomenon. This phenomenon will be described in detail with reference to FIGS. 3 and 4, in which FIG. 4 shows an equivalent circuit for explaining the thyristor effect.
In this CMOS transistor, a parasitic npn transistor Qn and a parasitic pnp transistor Qp are formed. The parasitic npn transistor Qn has the n.sup.+ -type source region 27.sub.2 of the n-channel MOS transistor as an emitter, the p-well 25 as a base and the n.sup.- -type silicon layer 23 as a collector. The parasitic pnp transistor Qp has the p.sup.+ -type source region 27.sub.1 as an emitter, the n.sup.- -type silicon layer 23 as a base and the p-well 25 as a collector. On the other hand, when the source regions 27.sub.1 and 27.sub.2 and the drain regions 28.sub.1 and 28.sub.2 of the respective MOS transistors are micropatterned along with an increase in packing density of the CMOS-ICs, electrons are generated by impact ionization in the vicinity of the drain region 28.sub.1 when the p-channel MOS transistor is turned on. These electrons are reflected by the interface between the n.sup.+ -type IG wafer 21 and the n.sup.- -type silicon layer 23 and are returned to the silicon layer 23. As described with reference to FIG. 2, the electrons will not be trapped by the microdefects in the IG wafer 21. A potential at the n.sup.- -type silicon layer 23 is decreased, and then the parasitic pnp transistor Qp having the n.sup.- -type silicon layer 23 as the base is subjected to bipolar action. As a result, a collector current I.sub.RW of the transistor Qp flows through the p-well 25. More specifically, the collector current I.sub.RW flows through a resistor R.sub.W at the V.sub.SS side of the p-well 25, thereby increasing the bias voltage to the base of the parasitic npn transistor Qn. As a result, the parasitic npn transistor Qn is subjected to bipolar action. A collector current I.sub.RS of the parasitic transistor Qp flows in the n.sup.- -type silicon layer 23 to lower the potential at the base of the parasitic pnp transistor Qp. Even if impact ionization no longer occurs, the transistor Qp is subjected to bipolar action since the base potential thereof is lowered. The collector current I.sub.RW increases the potential at the base of the parasitic npn transistor Qn so that the collector current I.sub.RS of the transistor Qn easily flows, thereby further lowering the base potential of the parasitic pnp transistor Qp and increasing the base potential of the transistor Qp. According to this positive feedback, a large current flows from the V.sub.DD terminal to the V.sub.SS terminal, as shown in FIG. 4. In addition to the disadvantage that the CMOS can become inoperative due to the latch-up current, the CMOS-IC as a whole can be thermally damaged by the large current. In the above operation, when the n-channel MOS transistor is simultaneously turned on, holes are generated by impact ionization in the vicinity of the drain region 28.sub.2, thereby increasing the potential at the p-well 25 and hence causing a larger current to flow from the V.sub.DD terminal to the V.sub.SS terminal, in addition to the effect described above.